Personal tools
Jump to: navigation, search

Jennifer M. Jayme

(MS Graduated: 1st Sem 2008-2009)

Abstract

High performance processor architectures are moving towards designs that feature multiple processing cores on a single chip. Multicore systems are characterized by high traffic levels from multiple resources. Performance and scalability can greatly depend on the robustness of the system’s interconnect and its ability to optimally manage access to and from the resources. By using a bus network, extension of multiple CPUs to multiple resources can be achieved in the simplest and least costly way.

The effectiveness of a bus-based interconnect scheme is investigated in this paper, using an Advanced Microcontroller Bus Architecture (AMBA) Advanced High Performance Bus (AHB multiprocessor system. Four bus structures were examined namely, Single Bus (SB), Multiple Bus (MB), Processor-Oriented Partial Multiple Bus (PPMB) and Memory-Oriented Partial Multiple Bus (MPMB).

For the two, four and eight processor-memory sets, the PPMB configuration was realized as the best bus-based interconnect setup for the ARM7 microprocessor. It gave a 400% improvement in cycles per instruction compared to the least expensive SB scheme, for an area overhead of 22%. Weighed against the fastest MB and a slower MPMB, PPMB gave a 2% smaller area difference at an expense of 3% in speed compared to MB.

Subject Index : Microcomputers -- Buses

  • This page was last modified on 3 February 2012, at 16:35.
  • This page has been accessed 1,212 times.
The Fine Print: contents on this site are owned by whoever posted them (as indicated on the page History). Neither the DILC nor the University is responsible for them in any way. DILC reserves the right to delete them if they are deemed in violation of the University's Acceptable Use Policy and other applicable laws.